MCIMX27VOP4 Datasheet, PDF (72/118 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Table 36. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID
SD9
SD10
Parameter
Data out hold time¹
Active to read/write command period
Symbol
Min
Max
Unit
tOH
1.8
—
ns
tRC
10
—
clock
1 _{Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see}
Table 40 and Table 41.
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 36 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
i.MX27 Data Sheet, Advance Information, Rev. 0.1
72
Preliminary—Subject to Change Without Notice
Freescale Semiconductor