MCIMX27VOP4 Datasheet, PDF (54/118 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Number
3
4
5
6
Table 21. Non-Gated Clock Mode Parameters (continued)
Parameter
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk high time
Minimum
1
THCLK
THCLK
0
Maximum
—
—
—
HCLK/2
Unit
ns
ns
ns
MHz
HCLK = AHB System Clock, THCLK = Period of HCLK
3.5.6 Configurable Serial Peripheral Interface (CSPI)
This section describes the electrical information of the CSPI.
3.5.6.1 CSPI Timing
Figure 13 and Figure 14 show the master mode and slave mode timings of CSPI, and Table 22 lists the
timing parameters.
SSn _(output)
CSPI1_RDY(input)
t1 _t2
t5
t3 ^t4
SCLK, MOSI, MISO
Figure 13. CSPI Master Mode Timing Diagram
SSn (input)
SCLK, MOSI, MISO
t6
t7
t8
Figure 14. CSPI Slave Mode Timing Diagram
i.MX27 Data Sheet, Advance Information, Rev. 0.1
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor