MCIMX27VOP4 Datasheet, PDF (53/118 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

1
VSYNC
PIXCLK
Signal Descriptions
6
4
5
DATA[7:0]
Valid Data
2
3
Valid Data
Valid Data
Figure 11. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Falling Edge,
Latch Data at Rising Edge
Figure 12 shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock
falling edge.
1
VSYNC
6
5
4
PIXCLK
DATA[7:0]
Valid Data
2
3
Valid Data
Valid Data
Figure 12. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Rising Edge,
Latch Data at Falling Edge
Table 21. Non-Gated Clock Mode Parameters
Number
1
2
Parameter
csi_vsync to csi_pixclk
csi_d setup time
Minimum
9*THCLK
1
Maximum
—
—
Unit
ns
ns
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53