33975 Datasheet, PDF (9/32 Pages) Freescale Semiconductor, Inc – Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current

DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ V_PWR ≤ 28 V, -40°C ≤ T_C ≤ 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V_PWR = 13 V, T_A = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
Interrupt Delay Time
Normal Mode
t _{pulse (on)}
15
16
22
ms
t _int-dly
µs
–
5.0
16
Sleep Mode Switch Scan Time
Calibrated Scan Timer Accuracy
Sleep Mode
t_scan
100
200
300
µs
t_{scan timer}
–
%
–
10
Calibrated Interrupt Timer Accuracy
Sleep Mode
DIGITAL INTERFACE TIMING ⁽¹²⁾
t_{int timer}
–
%
–
10
Required Low State Duration on VPWR for Reset ⁽¹³⁾
V_PWR ≤ 0.2 V
t _RESET
–
µs
–
10
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t _lead
100
–
ns
–
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t _lag
ns
50
–
–
SI to Falling Edge of SCLK
Required Setup Time
t _{SI (su)}
16
–
ns
–
Falling Edge of SCLK to SI
Required Hold Time
t _{SI (hold)}
20
–
ns
–
SI, CS, SCLK Signal Rise Time ⁽¹⁴⁾
t _{r (SI)}
–
5.0
–
ns
SI, CS, SCLK Signal Fall Time ⁽¹⁴⁾
t _f(SI)
–
5.0
–
ns
Time from Falling Edge of CS to SO Low Impedance ⁽¹⁵⁾
t _{SO (en)}
–
–
55
ns
Time from Rising Edge of CS to SO High Impedance ⁽¹⁶⁾
t _{SO (dis)}
–
–
55
ns
Time from Rising Edge of SCLK to SO Data Valid ⁽¹⁷⁾
t _valid
–
25
55
ns
Notes
12. These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
13. This parameter is guaranteed by design but not production tested.
14. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
15. Time required for valid output status data to be available on SO terminal.
16. Time required for output states data to be terminated at SO terminal.
17. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33975
9