MCIMX25_1 Datasheet, PDF (81/132 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

Table 56. ESAI General Timing Requirements (continued)
No.
Characteristics^{1 2}
Symbol
Expression³
Min. Max. Condition Unit
86 SCKT rising edge to data out valid
—
—
— 18.0
x ck
ns
— 13.0
i ck
87 SCKT rising edge to data out high
impedance⁶
—
—
— 21.0
x ck
ns
— 16.0
i ck
88 SCKT rising edge to transmitter #0 drive
—
enable negation⁶
—
— 14.0
x ck
ns
— 9.0
i ck
89 FST input (bl, wr) setup time before SCKT
—
falling edge⁵
—
2.0 —
x ck
ns
18.0 —
i ck
90 FST input (wl) setup time before SCKT falling —
edge
—
2.0 —
x ck
ns
18.0 —
i ck
91 FST input hold time after SCKT falling edge —
—
4.0 —
x ck
ns
5.0 —
i ck
92 FST input (wl) to data out enable from high
—
impedance
—
— 21.0
—
ns
93 FST input (wl) to transmitter #0 drive enable —
assertion
—
— 14.0
—
ns
94 Flag output valid after SCKT rising edge
—
—
— 14.0
x ck
ns
— 9.0
i ck
95 HCKR/HCKT clock cycle
—
96 HCKT input rising edge to SCKT output
—
2 x T_C
15 —
—
ns
—
— 18.0
—
ns
97 HCKR input rising edge to SCKR output
—
—
— 18.0
—
ns
1 _{VCORE_VDD = 1.00 ± 0.10 V; TJ = –40 °C to 125 °C, CL = 50 pF}
2 _{In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative}
3 _{In the “Expression” column, TC = 7.5 ns.}
4 _{For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.}
5 _{The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync}
signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal),
until the second-to-last bit-clock of the first word in the frame.
6 _{Periodically sampled and not 100% tested.}
3.6.8 Enhanced Secured Digital Host Controller (eSDHCv2) Timing
Figure 54 shows eSDHCv2 timing, and Table 57 describes the timing parameters (SD1–SD8) used in the
figure. The following definitions apply to values and signals described in Table 57:
• LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz
• FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card
clock can reach 25 MHz
• HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can
reach 50 MHz
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
81