MCIMX25_1 Datasheet, PDF (79/132 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

Figure 53 shows the ESAI HCKR timing diagram.
HCKR
95
SCKR (output)
97
Figure 53. ESAI HCKR Timing
Table 56 describes the general timing requirements for the ESAI module. Table 54 and Table 55 describe
respectively the conditions and signals cited in Table 56.
Table 54. ESAI Timing Conditions
Symbol
Significance
Comments
i ck
x ck
i ck a
Internal clock
In the i.MX25, the internal clock frequency is equal to the IP bus frequency
(133 MHz)
External clock
The external clock may be derived from the CRM module or other external
clock sources
Internal clock, asynchronous mode In asynchronous mode, SCKT and SCKR are different clocks
i ck s Internal clock, synchronous mode In synchronous mode, SCKT and SCKR are the same clock
SCKT
SCKR
FST
HCKT
HCKR
Signal Name
Table 55. ESAI Signals
Transmit clock
Receive clock
Transmit frame sync
Transmit high-frequency clock
Receive high-frequency clock
Significance
Table 56. ESAI General Timing Requirements
No.
Characteristics^{1 2}
62 Clock cycle⁴
63 Clock high period
For internal clock
For external clock
64 Clock low period
For internal clock
For external clock
Symbol
t_SSICC
—
—
—
—
—
Expression³
4 × T_c
4 × T_c
—
2 × T_c − 9.0
2 × T_c
2 × T_c − 9.0
2 × T_c
Min. Max. Condition Unit
30.0 —
30.0 —
—
—
6
—
i ck
ns
i ck
—
ns
15 —
6
—
—
—
ns
15 —
—
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
79