MCIMX25_1 Datasheet, PDF (107/132 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

3.6.17.4 SSI Receiver Timing with External Clock
Figure 81 shows the timing for SSI receiver with external clock. Table 80 describes the timing
parameters (SS22–SS41) used in the figure.
SS23
SS22
SS26
SS25
SS24
AUDn_TXC
(Input)
AUDn_TXFS (bl)
(Input)
AUDn_TXFS (wl)
(Input)
AUDn_RXD
(Input)
SS28
SS30
SS32
SS35
SS40
SS34
SS41
SS36
Figure 81. SSI Receiver with External Clock Timing Diagram
Table 80. SSI Receiver Timing with External Clock
ID
Parameter
Min.
Max.
Unit
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
External Clock Operation
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
FS (bl) low/high setup before (Tx) CK falling
FS (bl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
81.4
36.0
—
36.0
—
–10.0
10.0
–10.0
10.0
—
—
10.0
2.0
—
ns
—
ns
6.0
ns
—
ns
6.0
ns
15.0
ns
—
ns
15.0
ns
—
ns
6.0
ns
6.0
ns
—
ns
—
ns
Note:
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
• All timings are on pads when SSI is being used for data transfer.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
107