68HC05V12 Datasheet, PDF (81/240 Pages) Freescale Semiconductor, Inc – General Release Specification

READ $0006
WRITE $0006
WRITE $0002
RREAD $0002
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port C
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
I/O
OUTPUT
PIN
INTERNAL HC05
DATA BUS
RESET
(RST)
TO IRQ SUBSYSTEM
SEE FIGURE 4-2
Figure 7-3. Port C I/O Circuitry
7.5.1 Port C Data Register
Each port C I/O pin has a corresponding bit in the port C data register.
When a port C pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port C pin is programmed as an input, any read of the port C
data register will return the logic state of the corresponding I/O pin. The
port C data register is unaffected by reset.
7.5.2 Port C Data Direction Register
Each port C I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRC or programmed as an output by setting
the corresponding bit in the DDRC. The DDRC can be accessed at
address $0006 and is cleared by reset.
7.5.3 Port C I/O Pin Interrupts
The inputs of all eight bits of port C are ANDed into the IRQ input of the
CPU. See Figure 4-2. This port has its own interrupt request latch to
enable the user to differentiate between the IRQ sources. The port IRQ
MC68HC05V12 — Rev. 1.0
General Release Specification
Parallel Input/Output (I/O)
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