68HC05V12 Datasheet, PDF (61/240 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Interrupts
16-Bit Timer Interrupt
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-
only trigger is available as a mask option for the IRQ pin only.
4.8 16-Bit Timer Interrupt
Three different timer interrupt flags cause a 16-bit timer interrupt
whenever they are set and enabled. The interrupt flags are in the timer
status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
location $3FF8 and $3FF9.
4.9 BDLC Interrupt
The interrupt service routine is located at the address specified by the
contents of memory location $3FF6 and $3FF7.
4.10 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory location
$3FF4 and $3FF5.
4.11 8-Bit Timer Interrupt
This timer can create two types of interrupts. A timer overflow interrupt
will occur whenever the 8-bit timer rolls over from $FF to $00 and the
enable bit TOFE is set. A real-time interrupt will occur whenever the
programmed time elapses and the enable bit RTIE is set. This interrupt
will vector to the interrupt service routine located at the address specified
by the contents of memory location $3FF2 and $3FF3.
MC68HC05V12 — Rev. 1.0
General Release Specification
Interrupts
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