68HC05V12 Datasheet, PDF (172/240 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital
14.9.3 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in the
BCR register is previously clear.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BCR register is previously set. This results in saving less power,
but the BDLC is guaranteed to correctly receive the message which
woke it up, since the BDLC internal operating clocks are kept running.
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
MC68HC05V12 — Rev. 1.0