68HC05V12 Datasheet, PDF (151/240 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Byte Data Link Controller-Digital (BDLC-D)
BDLC Protocol Handler
14.7.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register.
The Tx shift register takes data, in parallel form, from the Tx shadow
register and presents it serially to the state machine so that it can be
transmitted onto the J1850 bus.
14.7.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set and interrupt is generated if the interrupt enable bit (IE) in
BCR1 is set. After the transfer takes place, this new data byte in the Rx
shadow register is available to the CPU interface, and the Rx shift
register is ready to shift in the next byte of data. Data in Rx shadow
register must be retrieved by the CPU before it is overwritten by new
data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU.
14.7.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RXP to TXP internally, when
the DLBE bit in BCR2 register is set.
14.7.5 State Machine
All functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com