33926 Datasheet, PDF (8/24 Pages) Freescale Semiconductor, Inc – 5.0 A Throttle Control H-Bridge

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ V_PWR ≤ 28 V, -40°C ≤ T_A ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency ⁽²¹⁾
Maximum Switching Frequency During Current Limit Regulation ⁽²²⁾
Output ON Delay ⁽²³⁾
V_PWR = 14 V
Output OFF Delay ⁽²³⁾
V_PWR = 14 V
I_LIM Output Constant-OFF Time ⁽²⁴⁾
I_LIM Blanking Time ⁽²⁵⁾
Disable Delay Time ⁽²⁶⁾
Output Rise and Fall Time ⁽²⁷⁾
SLEW = SLOW
SLEW = FAST
Short Circuit / Overtemperature Turn-OFF (Latch-OFF) Time ^{(28) (29)}
Power-ON Delay Time ⁽²⁹⁾
Output MOSFET Body Diode Reverse Recovery Time ⁽²⁹⁾
Charge Pump Operating Frequency ⁽²⁹⁾
f _PWM
–
f _MAX
–
t _DON
–
t _DOFF
–
t_A
15
t_B
12
t _DDISABLE
–
t _F, t _R
1.5
0.5
t _FAULT
–
t _POD
–
t_RR
75
f_CP
–
–
20
kHz
–
20
kHz
µs
–
18
µs
–
12
20.5
32
µs
16.5
27
µs
–
8.0
µs
µs
3.0
8.0
–
1.45
2.0
–
µs
1.0
5.0
ms
100
150
ns
7.0
–
MHz
Notes
21. The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to
SLOW should be limited to frequencies < 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side
MOSFETs.
22. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
23. * Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5V on the input signal to the 80% point of the
output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5V on the input signal to the 20% point of the output
response signal. See Figure 4, page 9.
24. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
25. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
26. * Disable Delay Time measurement is defined in Figure 5, page 9.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V_PWR = 14 V,
R_LOAD = 3.0 ohm. See Figure 6, page 9.
28. Load currents ramping up to the current regulation threshold become limited at the I_LIM value (see Figure 7). The short circuit currents
possess a di/dt that ramps up to the I_SCH or I_SCL threshold during the I_LIM blanking time, registering as a short circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to “fold back”,
or decrease, until ~175°C is reached, after which the T_LIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
29. Parameter is Guaranteed By Design.
33926
8
Analog Integrated Circuit Device Data
Freescale Semiconductor