33926 Datasheet, PDF (3/24 Pages) Freescale Semiconductor, Inc – 5.0 A Throttle Control H-Bridge

PIN CONNECTIONS
PIN CONNECTIONS
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IN2
IN1
SLEW
VPWR
AGND
VPWR
INV
FB
NC
1 32 31 30 29 28 27 26 25
2
24
3
23
4
22
5
AGND
21
6
20
7
19
8
18
9 10 11 12 13 14 15 16 17
NC
PGND
PGND
PGND
SF
PGND
PGND
PGND
NC
Figure 3. 33926 Pin Connections
Table 1. 33926 Pin Definitions
A functional description of each pin can be found in the Functional Description section beginning on page 11.
Pin
Pin
Pin Name _Function
Formal Name
Definition
1
IN2
Logic Input
Input 2
Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to V_PWR,
and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with
~ 80 µA source so default condition = OUT2 HIGH.)
2
IN1
Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to V_PWR,
and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with
~ 80 µA source so default condition = OUT1 HIGH.)
3
SLEW _{Logic Input}
Slew Rate
Logic input to select fast or slow slew rate. (Schmitt trigger input with ~ 80 µA
sink so default condition = slow.)
4, 6, 11, 31
5,
Exposed
Pad
7
VPWR
AGND
INV
Power Input
Analog
Ground
Logic Input
Positive Power
Supply
Analog Signal
Ground
Input Invert
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
The low current analog signal ground must be connected to PGND via low
impedance path (<<10 mΩ, 0 Hz to 20 kHz). Exposed copper pad is also the
main heatsinking path for the device.
Sets IN1 and IN2 to logic LOW = TRUE. (Schmitt trigger input with ~ 80 µA sink
so default condition = non-inverted.)
8
9, 17, 25
10
FB
Analog
Feedback
Load current feedback output provides ground referenced 0.24% of H-Bridge
Output
high-side output current. (Tie pin to GND through a resistor if not used.)
NC
No Connect
No internal connection is made to this pin.
EN
Logic Input ^{Enable Input}
When EN is logic HIGH, the device is operational. When EN is logic LOW, the
device is placed in Sleep mode. (logic input with ~ 80 µA sink so default
condition = Sleep mode.)
Analog Integrated Circuit Device Data
Freescale Semiconductor
33926
3