MC9S12XF512 Datasheet, PDF (790/1300 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 16 S12X Debug (S12XDBGV3) Module
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the
S12XDBG module is designed to help find.
NOTE
In certain very tight loops, the source address will have already been fetched
again before the background comparator is updated. This results in the
source address being stored twice before further duplicate entries are
suppressed. This condition occurs with branch-on-bit instructions when the
branch is fetched by the first P-cycle of the branch or with loop-construct
instructions in which the branch is fetched with the first or second P cycle.
See examples below:
LOOP
INX
BRCLR
CMPTMP,#$0c, LOOP
; 1-byte instruction fetched by 1st P-cycle of BRCLR
; the BRCLR instruction also will be fetched by 1st
; P-cycle of BRCLR
LOOP2
BRN
NOP
DBNE
*
A,LOOP2
; 2-byte instruction fetched by 1st P-cycle of DBNE
; 1-byte instruction fetched by 2nd P-cycle of DBNE
; this instruction also fetched by 2nd P-cycle of DBNE
16.4.5.2.3 Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode is intended to supply additional information on indexed, indirect addressing modes where storing
only the destination address would not provide all information required for a user to determine where the
code is in error. This mode also features information byte entries to the trace buffer, for each address byte
entry. The information byte indicates the size of access (word or byte) and the type of access (read or
write).
When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is
either in a free or opcode fetch cycle, the address range can be limited to a range specified by the TRANGE
bits in DBGTCR. This function uses comparators C and D to define an address range inside which
CPU12X activity should be traced (see Table 16-39). Thus the traced CPU12X activity can be restricted
to particular register range accesses.
16.4.5.2.4 Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal
opcodes, are stored.
16.4.5.3 Trace Buffer Organization
Referring to Table 16-39. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.
INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst
tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]
MC9S12XF - Family Reference Manual, Rev.1.18
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