MC9S12XF512 Datasheet, PDF (599/1300 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 13 FlexRay Communication Controller (FLEXRAY)
PE Clock
Strobe Signal
FlexRay Bus Event
+4
Figure 13-141. Strobe Signal Timing (type = pulse, clk_offset = +4)
13.6.17 Timer Support
The FlexRay block provides two timers, which run on the FlexRay time base. Each timer generates a
maskable interrupt when it reaches a configured point in time. Timer T1 is an absolute timer. Timer T2 can
be configured to be an absolute or a relative timer. Both timers can be configured to be repetitive. In the
non-repetitive mode, timer stops if it expires. In repetitive mode, timer is restarted when it expires.
Both timers are active only when the protocol is in POC:normal active or POC:normal passive state. If
the protocol is not in one of these modes, the timers are stopped. The application must restart the timers
when the protocol has reached the POC:normal active or POC:normal passive state.
13.6.17.1 Absolute Timer T1
The absolute timer T1 has the protocol cycle count and the macrotick count as the time base. The timer 1
interrupt flag TI1_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set at the macrotick start event,
if Equation 13-25 and Equation 13-26 are fulfilled
CYCCTR.CYCCNT & T1CYSR.T1_CYC_MSK == T1CYSR.T1_CYC_VAL & T1CYSR.T1_CYC_MSKEqn. 13-25
MTCTR.MTCT == TI1MTOR.T1_MTOFFSET
Eqn. 13-26
If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 (PIER0) is asserted,
an interrupt request is generated.
The status bit T1ST is set when the timer is triggered, and is cleared when the timer expires and is non-
repetitive. If the timer expires but is repetitive, the T1ST bit is not cleared and the timer is restarted
immediately. The T1ST is cleared when the timer is stopped.
13.6.17.2 Absolute / Relative Timer T2
The timer T2 can be configured to be an absolute or relative timer by setting the T2_CFG control bit in the
Timer Configuration and Control Register (TICCR). The status bit T2ST is set when the timer is triggered,
and is cleared when the timer expires and is non-repetitive. If the timer expires but is repetitive, the T2ST
bit is not cleared and the timer is restarted immediately. The T2ST is cleared when the timer is stopped.
13.6.17.2.1 Absolute Timer T2
If timer T2 is configured as an absolute timer, it has the same functionality timer T1 but the configuration
from Timer 2 Configuration Register 0 (TI2CR0) and Timer 2 Configuration Register 1 (TI2CR1) is used.
MC9S12XF - Family Reference Manual, Rev.1.18
Freescale Semiconductor
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