MC9S12XF512 Datasheet, PDF (410/1300 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 11 Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
Table 11-5. MMCCTL0 Field Descriptions
Field
Description
7–6
CS3E[1:0]
5–4
CS2E[1:0]
3–2
CS1E[1:0]
1–0
CS0E[1:0]
Chip Select 3 Enables — These bits enable the external chip select CS3 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 3 is disabled
01,10,11 Chip select 3 is enabled
Chip Select 2 Enables — These bits enable the external chip select CS2 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 2 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 2 is disabled
01,10,11 Chip select 2 is enabled
Chip Select 1 Enables — These bits enable the external chip select CS1 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 1 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 1 is disabled
01,10,11 Chip select 1 is enabled
Chip Select 0 Enables — These bits enable the external chip select CS0 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 0 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 0 is disabled
01,10,11 Chip select 0 is enabled
Table 11-6 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Table 11-6. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
CS2⁽²⁾
0x00_0800
0x14_0000
0x0F_FFFF minus RAMSIZE⁽¹⁾
0x1F_FFFF
CS1
0x20_0000
0x3F_FFFF
CS0⁽³⁾
0x40_0000
1. External RPAGE accesses in (NX, EX)
0x7F_FFFF minus FLASHSIZE⁽⁴⁾
2. When ROMHM is set (see ROMHM in Table 11-15) the CS2 is asserted in the space occupied by this on-
chip memory block.
3. When the internal NVM is enabled (see ROMON in Section 11.3.2.5, “MMC Control Register (MMCCTL1))
the CS0 is not asserted in the space occupied by this on-chip memory block.
4. External PPAGE accesses in (NX, EX)
MC9S12XF - Family Reference Manual, Rev.1.18
412
Freescale Semiconductor