MC9RS08KA2_08 Datasheet, PDF (79/136 Pages) Freescale Semiconductor, Inc – RS08 Microcontrollers

9.3.3 ICS Trim Register (ICSTRM)
Internal Clock Source (RS08ICSV1)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-4. ICSTRM Field Descriptions
Field
7:0
TRIM
Description
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
9.3.4 ICS Status and Control (ICSSC)
7
R
0
W
6
5
4
0
0
0
3
2
1
0
0
CLKST
0
FTRIM
POR:
0
0
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
0
U
= Unimplemented
Figure 9-6. ICS Status and Control Register (ICSSC)
Table 9-5. ICSSC Field Descriptions
Field
2
CLKST
0
FTRIM
Description
Clock Mode Status — The CLKST read-only bit indicate the current clock mode. The CLKST bit does not update
immediately after a write to the CLKS bit due to internal synchronization between clock domains.
0 Output of FLL is selected
1 Internal reference clock is selected
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
79