MC9RS08KA2_08 Datasheet, PDF (49/136 Pages) Freescale Semiconductor, Inc – RS08 Microcontrollers

Chapter 6 Parallel Input/Output Control
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
PTASE5
PTASE4
PTASE3
PTASE1
0
1
1
1
0
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-5. PTASE Register Field Descriptions
0
PTASE0
1
Field
Description
5:3;1:0
Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew
PTASE[5:3;1:0] rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
49