MC9RS08KA2_08 Datasheet, PDF (21/136 Pages) Freescale Semiconductor, Inc – RS08 Microcontrollers

Chapter 3
Modes of Operation
3.1 Introduction
This chapter describes the operating modes of the MC9RS08KA2 Series are described in this chapter. It
also details entry into each mode, exit from each mode, and functionality while in each of the modes.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU shuts down to conserve power
— System clocks continue to run
— Full voltage regulation is maintained
• Stop mode:
— System clocks are stopped; voltage regulator in standby
— All internal circuits remain powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9RS08KA2 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address $3FFD. A JMP instruction (opcode $BC) with operand
located at $3FFE–$3FFF must be programmed for correct reset operation into the user application. The
operand defines the location at which the user program will start. Instead of using the vector fetching
process as in HC08/S08 families, the user program is responsible for performing a JMP instruction to
relocate the program counter to the correct user program start location.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the RS08 core. The BDC provides the means for analyzing MCU operation during software development.
Active background mode is entered in any of four ways:
• When the BKGD/MS pin is low during power-on-reset (POR) or immediately after issuing a
background debug force reset (BDC_RESET) command
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
21