MCIMX35_101 Datasheet, PDF (71/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

Table 52. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min.
IP16 Display interface clock low time
IP17 Display interface clock high time
IP18 Data setup time
IP19 Data holdup time
IP20 Control signals setup time to
display interface clock
Tckl Tdicd – Tdicu – 1.5
Tckh Tdicp – Tdicd +
Tdicu – 1.5
Tdsu Tdicd – 3.5
Tdhd Tdicp – Tdicd – 3.5
Tcsu Tdicd – 3.5
Typ.¹
Tdicd² – Tdicu³
Tdicp – Tdicd +
Tdicu
Tdicu
Tdicp – Tdicu
Tdicu
Max.
Tdicd – Tdicu + 1.5
Tdicp – Tdicd +
Tdicu + 1.5
—
—
—
Units
ns
ns
ns
ns
ns
1 _{The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.}
These conditions may be device specific.
2 _{Display interface clock down time}
Tdicd
=
1--
2
THSP_CLK
⋅
ceil
2-----⋅_{---D----I--S----P---3---_---I--F---_---C----L----K----_---D-----O----W------N----_---W------R--}
HSP_CLK_PERIOD
3 _{Display interface clock up time}
Tdicu
=
1--
2
THSP_CLK
⋅
ce
il
-2----^â‹---D----I--S----P---3---_---I--F---_---C----L----K----_---U-----P---_---W------R--
HSP_CLK_PERIOD
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
4.9.13.2 Interface to Sharp HR-TFT Panels
Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 53 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8
Freescale Semiconductor
71