MCIMX35_101 Datasheet, PDF (105/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

Figure 82. UDMA-In Device Terminates Transfer Timing Diagram
Table 68. UDMA-In Burst Timing Parameters
ATA
Parameter
Parameters
from
Figure 80,
Figure 81,
Figure 82
Description
Controlling Variable
tack
tack
tack (min.) = (time_ack × T) – (tskew1 + tskew2)
tenv
tenv
tenv (min.) = (time_env × T) – (tskew1 + tskew2)
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
time_ack
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tdh
tdh1
tdh – (tskew3) – ti_dh > 0
tskew3, ti_ds, ti_dh
should be low enough
tcyc
trp
—
tmli
tzah
tdzfs
tcvh
—
tc1
trp
tx1¹
tmli1
tzah
tdzfs
tcvh
ton
toff
(tcyc – tskew > T
trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6)
(time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive)
tmli1 (min.) = (time_mlix + 0.4) × T
tzah (min.) = (time_zah + 0.4) × T
tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
tcvh = (time_cvh × T) – (tskew1 + tskew2)
ton = time_on × T – tskew1
toff = time_off × T – tskew1
T big enough
time_rp
time_rp
time_mlix
time_zah
time_dzfs
time_cvh
—
1 _{There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active}
edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff large enough to avoid bus contention.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8
Freescale Semiconductor
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