MCIMX35_101 Datasheet, PDF (14/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

4.2 Power Modes
Table 9 provides descriptions of the power modes of the i.MX35 processor.
Table 9. i.MX35 Power Modes
Power
Mode
Description
Wait
Doze
Stop
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
RNGC internal osc is off.
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300 Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
RNGC internal osc is off
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
QVCC (ARM/L2
Peripheral)
Typ.
Max.
MVDD/PVDD
Typ.
Max.
16 mA
—
7.2 mA
—
12.4 mA —
7.2 mA
—
1.1 mA
—
400 µA
—
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
1.2 mA
—
1.2 mA
—
1.2 mA
—
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8
14
Freescale Semiconductor