MCIMX35_101 Datasheet, PDF (40/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

Figure 22 through Figure 26, and Table 31 help to determine timing parameters relative chip select (CS)
state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing
parameters mentioned above.
CS [x]
ADDR
RW
LBA
OE
EB[y]
DATA
W E31
Last Valid Address
Address V1
WE32
Next Address
WE39
WE40
WE35
WE36
WE37
WE38
WE44
V1
WE43
Figure 22. Asynchronous Memory Read Access
CS[x]
ADDR/
M_DATA
WE
LBA
OE
BE[y]
WE31
Addr. V1
WE32A
MAXDI
D(V1)
WE39
WE35A
WE37
MAXCO
WE40
WE36
WE38
WE44
Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8
40
Freescale Semiconductor