K50P81M72SF1 Datasheet, PDF (70/78 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Pinout
8.1 K50 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
E7 — VDD
VDD
VDD
F7 — VSS
VSS
VSS
E6 1 VDD
VDD
VDD
G7 2 VSS
VSS
VSS
L6 — VSS
VSS
VSS
F1 3 USB0_DP USB0_DP USB0_DP
F2 4 USB0_DM USB0_DM USB0_DM
G1 5 VOUT33 VOUT33 VOUT33
G2 6 VREGIN VREGIN VREGIN
H1 7 ADC0_DP1/ ADC0_DP1/ ADC0_DP1/
OP0_DP0 OP0_DP0 OP0_DP0
H2 8 ADC0_DM1/ ADC0_DM1/ ADC0_DM1/
OP0_DM0 OP0_DM0 OP0_DM0
J1 9 ADC1_DP1/ ADC1_DP1/ ADC1_DP1/
OP1_DP0/ OP1_DP0/ OP1_DP0/
OP1_DM1 OP1_DM1 OP1_DM1
J2 10 ADC1_DM1/ ADC1_DM1/ ADC1_DM1/
OP1_DM0 OP1_DM0 OP1_DM0
K1 11 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
K2 12 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
L1 13 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
L2 14 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
F5 15 VDDA
VDDA
VDDA
G5 16 VREFH
VREFH
VREFH
G6 17 VREFL
VREFL
VREFL
F6 18 VSSA
VSSA
VSSA
J3 19 ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
OP1_OUT/ OP1_OUT/ OP1_OUT/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22/ ADC0_SE22/ ADC0_SE22/
OP0_DP2/ OP0_DP2/ OP0_DP2/
OP1_DP2 OP1_DP2 OP1_DP2
K50 Sub-Family Data Sheet, Rev. 2, 4/2012.
70
Freescale Semiconductor, Inc.