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K50P81M72SF1 Datasheet, PDF (24/78 Pages) Freescale Semiconductor, Inc – K50 Sub-Family | |||
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Peripheral operating requirements and behaviors
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 12. JTAG voltage range electricals
Symbol
J1
J2
J3
Description
Operating voltage
TCLK frequency of operation
⢠JTAG
⢠CJTAG
TCLK cycle period
TCLK clock pulse width
⢠JTAG
⢠CJTAG
Min.
2.7
â
â
1/J1
100
200
J4
TCLK rise and fall times
â
J5
TMS input data setup time to TCLK rise
⢠JTAG
53
⢠CJTAG
112
J6
TDI input data setup time to TCLK rise
8
J7
TMS input data hold time after TCLK rise
⢠JTAG
3.4
⢠CJTAG
3.4
J8
TDI input data hold time after TCLK rise
3.4
J9
TCLK low to TMS data valid
⢠JTAG
â
⢠CJTAG
â
J10
TCLK low to TDO data valid
â
J11
Output data hold/invalid time after clock edge1
â
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
Max.
5.5
10
5
â
â
â
1
â
â
â
â
â
â
48
85
48
3
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K50 Sub-Family Data Sheet, Rev. 2, 4/2012.
24
Freescale Semiconductor, Inc.
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