K50P81M72SF1 Datasheet, PDF (20/78 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

General
Table 7. Capacitance attributes (continued)
Symbol
C_{IN_D}
Description
Input capacitance: digital pins
Min.
Max.
Unit
—
7
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol Description
Normal run mode
f_SYS
System and core clock
f_{SYS_USB}
System and core clock when Full Speed USB in
operation
f_BUS
Bus clock
FB_CLK FlexBus clock
f_FLASH
Flash clock
f_LPTMR
LPTMR clock
VLPR mode¹
f_SYS
System and core clock
f_BUS
Bus clock
FB_CLK FlexBus clock
f_FLASH
Flash clock
f_ERCLK
External reference clock
f_{LPTMR_pin} LPTMR clock
f_{LPTMR_ERCLK} LPTMR external reference clock
f_{FlexCAN_ERCLK} FlexCAN external reference clock
f_{I2S_MCLK} I2S master clock
f_{I2S_BCLK}
I2S bit clock
Min.
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
72
—
50
50
25
25
4
4
4
1
16
25
16
8
12.5
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
K50 Sub-Family Data Sheet, Rev. 2, 4/2012.
20
Freescale Semiconductor, Inc.