K50P81M72SF1 Datasheet, PDF (48/78 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Peripheral operating requirements and behaviors
Table 28. 16-bit ADC with PGA characteristics (continued)
Symbol
E_IL
Description
Input leakage
error
Conditions
All modes
Min.
Typ.¹
I_In × R_AS
Max.
Unit
mV
V_PP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
THD
Total harmonic
distortion
• Gain=1
• Gain=64
• Gain=1
• Gain=64
V
where V_X = V_REFPGA × 0.583
80
90
—
dB
52
66
—
dB
85
100
—
dB
49
95
—
dB
SFDR
Spurious free
dynamic range
• Gain=1
• Gain=64
85
105
—
dB
53
88
—
dB
ENOB
Effective number
of bits
• Gain=1, Average=4
• Gain=64, Average=4
11.6
13.4
—
bits
7.2
9.6
—
bits
• Gain=1, Average=32
12.8
14.5
—
bits
• Gain=2, Average=32
11.0
14.3
—
bits
• Gain=4, Average=32
7.9
13.8
—
bits
• Gain=8, Average=32
7.3
13.1
—
bits
• Gain=16, Average=32
6.8
12.5
—
bits
• Gain=32, Average=32
6.8
11.5
—
bits
• Gain=64, Average=32
7.5
10.6
—
bits
Notes
I_In = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
6
16-bit
differential
mode,
Average=32
16-bit
differential
mode,
Average=32,
f_in=100Hz
16-bit
differential
mode,
Average=32,
f_in=100Hz
16-bit
differential
mode,f_in=100H
z
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume V_DDA =3.0V, Temp=25°C, f_ADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (V_CM) and the PGA gain.
4. _{Gain = 2}^PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
K50 Sub-Family Data Sheet, Rev. 2, 4/2012.
48
Freescale Semiconductor, Inc.