K50P81M72SF1 Datasheet, PDF (25/78 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

TCLK (input)
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Peripheral operating requirements and behaviors
J2
J3
J3
J4
J4
Figure 6. Test clock input timing
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 7. Boundary scan (JTAG) timing
K50 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
25