MC68020FE33E Datasheet, PDF (69/306 Pages) Freescale Semiconductor, Inc – MICROPROCESSORS USER’S MANUAL

Freescale Semiconductor, Inc.
Table 5-7. Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports
Data Bus Active Sections
Byte (B), Word (W) , Long-Word (L) Ports
Transfer Size
SIZ1 SIZ0 A1
A0
D31–D24
D23–D16
D15–D8
D7–D0
Byte
0
1
0
0
BWL
—
—
—
0
1
0
1
B
WL
—
—
0
1
1
0
BW
—
L
—
0
1
1
1
B
W
—
L
Word
1
0
0
0
BWL
WL
—
—
1
0
0
1
B
WL
L
—
1
0
1
0
BW
W
L
L
1
0
1
1
B
W
—
L
3 Bytes
1
1
0
0
BWL
WL
L
—
1
1
0
1
B
WL
L
L
1
1
1
0
BW
W
L
L
1
1
1
1
B
W
—
L
Long Word
0
0
0
0
BWL
WL
L
L
0
0
0
1
B
WL
L
L
0
0
1
0
BW
W
L
L
0
0
1
1
B
W
—
L
Figure 5-18 shows a logic diagram of one method for generating byte enable signals for
16- and 32-bit ports from the SIZ1, SIZ0, A1, and A0 encodings and the R/W signal.
5.2.5 Cache Interactions
The organization and requirements of the on-chip instruction cache affect the
interpretation of DSACK1 and DSACK0. Since the MC68020/EC020 attempts to load all
instructions into the on-chip cache, the bus may operate differently when caching is
enabled. Specifically, on read cycles that terminate normally, the A1, A0, SIZ1, and SIZ0
signals do not apply.
The cache can also affect the assertion of AS and the operation of a read cycle. The
search of the cache by the processor begins when the sequencer requires an instruction.
At this time, the bus controller may also initiate an external bus cycle in case the
requested item is not resident in the instruction cache. If an internal cache hit occurs, the
external cycle aborts, and AS is not asserted.
For the MC68020, if the bus is not occupied with another read or write cycle, the bus
controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have
ECS asserted on multiple consecutive clock cycles. Note that there is a minimum time
specified from the negation of ECS to the next assertion of ECS (refer to Section 10
Electrical Characteristics). Instruction prefetches can occur every other clock so that if,
after an aborted cycle due to an instruction cache hit, the bus controller asserts ECS on
the next clock, this second cycle is for a data fetch. Note that, if the bus controller is
executing other cycles, these aborted cycles due to cache hits may not be seen externally.
5-22
M68020 USER’S MANUAL
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