MC68020FE33E Datasheet, PDF (130/306 Pages) Freescale Semiconductor, Inc – MICROPROCESSORS USER’S MANUAL

Freescale Semiconductor, Inc.
ENTRY
S (SR)
M (SR)
T1, T0 (SR)
I2–I0 (SR)
VBR
CACR
1
0
0
$7
$00000000
$00000000
INSTRUCTION CACHE
ENTRIES INVALIDATED
FETCH VECTOR #0
OTHERWISE
SP (VECTOR #0)
BUS ERROR
FETCH VECTOR #1
OTHERWISE
PC (VECTOR #1)
BUS ERROR
PREFETCH 3 WORDS
OTHERWISE
BEGIN INSTRUCTION
EXECUTION
BUS ERROR OR
ADDRESS ERROR
EXIT
(DOUBLE BUS FAULT)
EXIT
(DOUBLE BUS FAULT)
EXIT
(DOUBLE BUS FAULT)
EXIT
Figure 6-1. Reset Operation Flowchart
The processor begins exception processing for a bus error by making an internal copy of
the current SR. The processor then enters the supervisor privilege level (by setting the S-
bit in the SR) and clears the T1 and T0 bits in the SR. The processor generates exception
vector number 2 for the bus error vector. It saves the vector offset, PC, and the internal
copy of the SR on the active supervisor stack. The saved PC value is the logical address
of the instruction that was executing at the time the fault was detected. This is not
necessarily the instruction that initiated the bus cycle since the processor overlaps
MOTOROLA
M68020 USER’S MANUAL
6-5
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