MC68020FE33E Datasheet, PDF (256/306 Pages) Freescale Semiconductor, Inc – MICROPROCESSORS USER’S MANUAL

Freescale Semiconductor, Inc.
MC68020/EC020
FC2–FC0
*^A31–A20
A19–A16
A15–A13
A12–A5
A4–A1
A0
AS
DS
R/W
D31–D24
D23–D16
D15–D8
D7–D0
DSACK0
DSACK1
CHIP
SELECT
DECODE
VCC
VCC
MC68881/MC68882
CS
SIZE
A4–A1
A0
AS
DS
R/W
D31–D24
D23–D16
D15–D8
D7–D0
DSACK0
DSACK1
MAIN PROCESSOR
CLOCK
* ^{For the MC68EC020, A23–A0.}
COPROCESSOR
CLOCK
Figure 9-1. 32-Bit Data Bus Coprocessor Connection
The chip select (CS) decode circuitry is asynchronous logic that detects when a particular
floating-point coprocessor is addressed. The MC68020/EC020 signals used by the logic
include FC2–FC0 and A19–A13. Refer to Section 7 Coprocessor Interface Description
for more information concerning the encoding of these signals. All or just a subset of these
lines may be decoded, depending on the number of coprocessors in the system and the
degree of redundant mapping allowed in the system.
For example, if a system has only one coprocessor, the full decoding of the ten signals
(FC2–FC0 and A19–A13), provided by the PAL equations in Figure 9-3, is not absolutely
necessary. It may be sufficient to use only FC1–FC0 and A17–A16. FC1–FC0 indicate
when a bus cycle is operating in either CPU space ($7) or user-defined space ($3), and
A17–A16 encode the CPU space type as coprocessor space ($2). A15–A13 can be
ignored in this case because they encode the coprocessor identification code (CpID) used
to differentiate between multiple coprocessors in a system. Motorola assemblers always
default to a CpID of $1 for floating-point instructions; this can be controlled with assembler
directives if a different CpID is desired or if multiple coprocessors exist in the system.
9-2
M68020 USER’S MANUAL
MOTOROLA
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