MC33905D Datasheet, PDF (671/766 Pages) Freescale Semiconductor, Inc – SBC Gen2 with CAN High Speed and LIN Interface

IEEE 1149.1 Test Access Port (JTAG)
Table 31-5. JTAG Instructions
Instruction
IR[3:0]
Instruction Summary
EXTEST
0000
Selects boundary scan register while applying fixed values to output pins and
asserting functional reset
IDCODE
0001 Selects IDCODE register for shift
SAMPLE/PRELOAD
TEST_LEAKAGE^1,2
0010
0101
Selects boundary scan register for shifting, sampling, and preloading without
disturbing functional operation
Selects bypass register while tri-stating all output pins and assert to high the
jtag_leakage signal
ENABLE_TEST_CTRL
0110 Selects TEST_CTRL register
HIGHZ
1001 Selects bypass register while tri-stating all output pins and asserting functional reset
LOCKOUT_RECOVERY 1011 Allows for the erase of the TFM flash when the part is secure
CLAMP
1100
Selects bypass while applying fixed values to output pins and asserting functional
reset
BYPASS
1111 Selects bypass register for data operations
Reserved
all others Decoded to select bypass register³
1_{Instruction for manufacturing purposes only}
2_{TRST pin assertion or power-on reset is required to exit this instruction.}
3_{Freescale reserves the right to change the decoding of the unused opcodes in the future.}
31.5.3.1 External Test Instruction (EXTEST)
The EXTEST instruction selects the boundary scan register. It forces all output pins and bidirectional pins
configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the
boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and
establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to
force a predictable internal state while performing external boundary scan operations.
31.5.3.2 IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the
TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and
other part identification data. The shift register LSB is forced to logic 1 on the rising edge of TCLK
following entry into the capture-DR state.Therefore, the first bit to be shifted out after selecting the
IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising
edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a
TAP reset, the IDCODE register is selected automatically.
31.5.3.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
• SAMPLE - obtain a sample of the system data and control signals present at the MCU input pins
and just before the boundary scan cell at the output pins. This sampling occurs on the rising edge
of TCLK in the capture-DR state when the IR contains the $2 opcode. The sampled data is
Freescale Semiconductor
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
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