MC33905D Datasheet, PDF (177/766 Pages) Freescale Semiconductor, Inc – SBC Gen2 with CAN High Speed and LIN Interface

Bit(s)
14–12
Name
MFD
Clock Module
Table 9-4. SYNCR Field Descriptions (continued)
Description
Multiplication Factor Divider. Contain the binary value of the divider in the PLL
feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference
frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL
loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one.
Note: In external clock mode, the MFD[2:0] bits have no effect.
((
The following table illustrates the system frequency multiplier of the reference
frequency¹ in normal PLL mode.
MFD[2:0]
000² 001 010 011 100 101 110 111
(4x) (6x) (8x)⁽³⁾ (10x) (12x) (14x) (16x) (18x)
000 (÷ 1)
001 (÷ 2)³
010 (÷ 4)
4
6
8 10 12 14 16 18
2
3
4
5
6
7
8
9
1 3/2 2 5/2 3 7/2 4 9/2
011 (÷ 8) 1/2 3/4 1 5/4 3/2 7/4 2 9/4
100 (÷ 16) 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8
101 (÷ 32) 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16
110 (÷ 64) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32
111 (÷ 128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64
1
f_sys
=
f--_r--e---f---×_-----2----(_{--M-----F----D------}+_-----2----)
2^RFD
;
f_ref × 2(MFD + 2) ≤ f_sys(max);
f_sys ≤ f_sys(max) ,
where f_sys(max) is the maximum system frequency for the particular MCF5282
device (66 MHz or 80 MHz).
2 _{MFD = 000 not valid for fref < 3 MHz}
3 _{Default value out of reset}
11
10–8
LOCRE
RFD
Loss-of-clock reset enable. Determines how the system handles a loss-of-clock
condition. When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in
SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an
immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared
before entering stop mode with the PLL disabled.
1 Reset on loss-of-clock
0 No reset on loss-of-clock
Note: In external clock mode, the LOCRE bit has no effect.
Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL
frequency divisor. See table in MFD bit description. Changing RFD[2:0] does not affect
the PLL or cause a relock delay. Changes in clock frequency are synchronized to the
next falling edge of the current system clock. To avoid surpassing the allowable system
operating frequency, write to RFD[2:0] only when the LOCK bit is set.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
9-7