MC33905D Datasheet, PDF (64/766 Pages) Freescale Semiconductor, Inc – SBC Gen2 with CAN High Speed and LIN Interface

ColdFire Core
FS[3:0]
00xx
0100
0101
011x
1000
1001
101x
1100
1101
111x
Table 2-7. Fault Status Encodings
Definition
Reserved
Error on instruction fetch
Reserved
Reserved
Error on operand write
Attempted write to write-protected space
Reserved
Error on operand read
Reserved
Reserved
• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the interrupt controller in case of an
interrupt. See Table 2-5.
2.3.4 Processor Exceptions
2.3.4.1 Access Error Exception
The exact processor response to an access error depends on the memory reference being performed. For
an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an
instruction for execution. Therefore, faults during instruction prefetches followed by a change of
instruction flow do not generate an exception. When the processor attempts to execute an instruction with
a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this
type of exception, the programming model has not been altered by the instruction generating the access
error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming
model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction
loading from memory, any registers already updated before the fault occurs contain the operands from
memory.
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
2-18
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor