MC33905D Datasheet, PDF (208/766 Pages) Freescale Semiconductor, Inc – SBC Gen2 with CAN High Speed and LIN Interface

Interrupt Controller Modules
NOTE
The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to
allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value
used by the interrupt controller must be in the range of 0–6.
• Second, the processor executes a STOP instruction which places it in stop mode. Once the
processor is stopped, each interrupt controller enables a special logic path which evaluates the
incoming interrupt sources in a purely combinatorial path; that is, there are no clocked storage
elements. If an active interrupt request is asserted and the resulting interrupt level is greater than
the mask value contained in LPICR[6:4], then each interrupt controller asserts the wake-up output
signal, which is routed to the SCM where it is combined with the wakeup signals from the other
interrupt controller and then to the PLL module to re-enable the device’s clock trees and resume
processing.
•
10-18
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor