MCF5282CVM66 Datasheet, PDF (640/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual

Debug Support
Commands transmitted to the debug module
Command code transmitted during this cycle
High-order 16 bits of memory address
Low-order 16 bits of memory address
Non-serial-related
activity
Sequence taken if operation
has not completed
READ (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
XXX
’NOT READY’
Next
Command
Code
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
XXX
MS RESULT
NEXT CMD
LS RESULT
Data used from this transfer
XXX
BERR
NEXT CMD
’NOT READY’
Sequence taken if illegal command
is received by debug module
Results from previous command
Sequence taken if bus error
occurs on memory access
Responses from the debug module
High- and low-order 16 bits of result
Figure 30-16. Command Sequence Diagram
The sequence is as follows:
• In cycle 1, the development system command is issued (READ in this example). The debug module
responds with either the low-order results of the previous command or a command complete status
of the previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
NOTE
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
• In cycle 3, the development system supplies the low-order 16 address bits. The debug module
always returns a not-ready response.
• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial
transfers that begin during a memory access return a not-ready response.
• Results are returned in the two serial transfer cycles after the memory access completes. For any
command performing a byte-sized memory read operation, the upper 8 bits of the response data are
undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is
sent to the debug module during the final transfer. If a memory or register access is terminated with
a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data.
30.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in Table 30-17.
30-22
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor