MCF5282CVM66 Datasheet, PDF (206/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual

Interrupt Controller Modules
Table 10-14. Interrupt Source Assignment for INTC1
Source Module Flag
Source Description
Flag Clearing Mechanism
1-7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27-63
Not Used
FLEX
CAN
BUF0I
BUF1I
Message buffer 0 interrupt
Message buffer 1 interrupt
Write BUF0I = 1 after reading BUF0I = 1
Write BUF1I = 1 after reading BUF1I = 1
BUF2I Message buffer 2 interrupt
Write BUF2I = 1 after reading BUF2I = 1
BUF3I Message buffer 3 interrupt
Write BUF3I = 1 after reading BUF3I = 1
BUF4I Message buffer 4 interrupt
Write BUF4I = 1 after reading BUF4I = 1
BUF5I Message buffer 5 interrupt
Write BUF5I = 1 after reading BUF5I = 1
BUF6I Message buffer 6 interrupt
Write BUF6I = 1 after reading BUF6I = 1
BUF7I Message buffer 7 interrupt
Write BUF7I = 1 after reading BUF7I = 1
BUF8I Message buffer 8 interrupt
Write BUF8I = 1 after reading BUF8I = 1
BUF9I Message buffer 9 interrupt
Write BUF9I = 1 after reading BUF9I = 1
BUF10I Message buffer 10 interrupt
Write BUF10I = 1 after reading BUF10I = 1
BUF11I Message buffer 11 interrupt
Write BUF11I = 1 after reading BUF11I = 1
BUF12I Message buffer 12 interrupt
Write BUF12I = 1 after reading BUF12I = 1
BUF13I Message buffer 13 interrupt
Write BUF13I = 1 after reading BUF13I = 1
BUF14I Message buffer 14 interrupt
Write BUF14I = 1 after reading BUF14I = 1
BUF15I Message buffer 15 interrupt
Write BUF15I = 1 after reading BUF15I = 1
ERR_INT Error interrupt
Write ERR_INT = 1 after reading ERR_INT = 1
BOFF_INT Bus-off interrupt
Write BOFF_INT = 1 after reading BOFF_INT = 1
WAKE_INT Wake-up interrupt
Write WAKE_INT = 1 after reading WAKE_INT = 1
Not used
10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt
controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives
in the interrupt controller, the controller examines all the currently-active level n interrupt requests,
determines the highest priority within the level, and then responds with the unique vector number
corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized
IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level
and priority number for the level into the IACKLPR register, where it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful
concept that allows an interrupt service routine to determine if there are other pending interrupts so that
the overhead associated with interrupt exception processing (including machine state save/restore
functions) can be minimized. In general, the software IACK is performed near the end of an interrupt
10-16
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor