MCF5282CVM66 Datasheet, PDF (632/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual

Debug Support
31
0
Field
Program Counter
Reset
—
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
the BDM port using the RDMREG and WDMREG commands using values shown in Section 30.5.3.3, “Command
Set Descriptions.”
DRc[4–0]
0x08 (PBR)
Figure 30-9. Program Counter Breakpoint Register (PBR)
Table 30-12 describes PBR fields.
Table 30-12. PBR Field Descriptions
Bits Name
Description
31–0 Address PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Figure 30-9 shows PBMR.
31
0
Field
Mask
Reset
—
R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
instruction and via the BDM port using the wdmreg command.
DRc[4–0]
0x09
Figure 30-10. Program Counter Breakpoint Mask Register (PBMR)
Table 30-13 describes PBMR fields.
Table 30-13. PBMR Field Descriptions
Bits Name
Description
31–0 Mask PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the
appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
30.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 30-11, configures the operation of the hardware breakpoint logic that
corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug
module. The TDR controls the actions taken under the defined conditions. Breakpoint logic may be
configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define
the first-level trigger.
30-14
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor