MCF5282CVM66 Datasheet, PDF (637/766 Pages) Freescale Semiconductor, Inc – MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual

.
16
15
S
Data Field [15:0]
Figure 30-13. Receive BDM Packet
Table 30-15 describes receive BDM packet fields.
Debug Support
0
Table 30-15. Receive BDM Packet Field Description
Bits Name
Description
16
S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be
ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a
new serial transfer after 32 processor clock periods.
S DataMessage
0 xxxxValid data transfer
0 0xFFFFStatus OK
1 0x0000Not ready with response; come again
1 0x0001Error—Terminated bus cycle; data invalid
1 0xFFFFIllegal command
15–0 D Data. Contains the message to be sent from the debug module to the development system. The
response message is always a single word, with the data field encoded as shown above.
30.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 30-14, consists of 16 data bits and 1 control bit.
16
15
0
C
D
Figure 30-14. Transmit BDM Packet
Table 30-16 describes transmit BDM packet fields.
Table 30-16. Transmit BDM Packet Field Description
Bits Name
Description
16 C Control. This bit is reserved. Command and data transfers initiated by the development system should
clear C.
15–0 D Data bits 15–0. Contains the data to be sent from the development system to the debug module.
30.5.3 BDM Command Set
Table 30-17 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of
each command. Issuing a BDM command when the processor is accessing debug module registers using
the WDEBUG instruction causes undefined behavior.
Freescale Semiconductor
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
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