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56F8323 Datasheet, PDF (62/140 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers | |||
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5.6.1 Interrupt Priority Register 0 (IPR0)
Base + $0
Read
Write
RESET
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
BKPT_U0 IPL STPCNT IPL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1 ReservedâBits 15â14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)â
Bits13â12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 1
⢠10 = IRQ is priority level 2
⢠11 = IRQ is priority level 3
5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)â
Bits 11â10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
⢠00 = IRQ disabled (default)
⢠01 = IRQ is priority level 1
⢠10 = IRQ is priority level 2
⢠11 = IRQ is priority level 3
5.6.1.4 ReservedâBits 9â0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2 Interrupt Priority Register 1 (IPR1)
Base + $1
Read
Write
RESET
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
RX_REG IPL TX_REG IPL TRBUF IPL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
56F8323 Technical Data, Rev. 17
62
Freescale Semiconductor
Preliminary
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