56F8323 Datasheet, PDF (104/140 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 8-3 GPIO External Signals Map (Continued)
GPIO Function
Peripheral
Function
GPIOB7
PHASEA0 / TA0
GPIOC0
GPIOC1
GPIOC2
GPIOC3
GPIOC4
GPIOC5
GPIOC6
EXTAL
XTAL
CAN_RX
CAN_TX
TC3
TC1 / RXD0
TC0 / TXD0
Package
Pin
52
46
47
61
62
63
64
1
Notes
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
Pull-ups default to disabled
Pull-ups default to disabled
CAN is NOT available in 56F8123
CAN is NOT available in 56F8123
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOX_PUR and
GPIOX_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values
of these registers.
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
56F8323 Technical Data, Rev. 17
104
Freescale Semiconductor
Preliminary