56F8323 Datasheet, PDF (5/140 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

56F8323/56F8123 General Description
Note: Features in italics are NOT available in the 56F8123 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• One FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 27 GPIO lines
• 64-pin LQFP Package
RESET
OCR_DIS V_CAP V_DD V_SS V_DDA V_SSA
5
4
44
2
3
3
6 _{PWM Outputs}
PWMA or
Current Sense Inputs SPI1 or
Fault Inputs
GPIOA
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Program Controller
Address
and Hardware Generation Unit
Looping Unit
Data ALU
16 x 16 + 36 −> 36-Bit MAC
Three 16-bit Input Registers
Bit
Manipulation
Unit
Four 36-bit Accumulators
4
AD0
4
AD1
Memory
XDB2
5
VREF
Program Memory
16K x 16 Flash
XAB1
XAB2
TEMP_SENSE _{2K x 16 RAM}
PAB
4K x 16 Boot
Flash
PDB
CDBR
Quadrature
Data Memory
CDBW
4
Decoder 0 or _{4K x 16 Flash}
Quad
4K x 16 RAM
Timer A or
GPIO B
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Quad
3
Timer C or
SCI0 or
GPIOC Decoding
Peripheral
Device Selects
RW IPAB IPWDB
Control
IPRDB
2
FlexCAN or ^Peripherals
GPIOC
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Interrupt
Watchdog Controller
IRQA
System
P
O
Integration ^R
Module
Clock
Generator*
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
*Includes On-Chip
Relaxation Oscillator
56F8323/56F8123 Block Diagram
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
5
Preliminary