56F8323 Datasheet, PDF (13/140 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC/PLL)
(ROSC)
Timer A
4
Quadrature Decoder 0
2
FlexCAN
4
2
SCI 1
SPI 0
GPIO A
GPIO B
GPIO C
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
SIM
RESET
COP Reset
COP
SPI 1
PWM A
SCI 0
4
8
SYNC Output
2
ch2i
3
Timer C
ch2o
ADCA
8
TEMP_SENSE
NOT available on the 56F8123 device.
IPBus
Figure 1-2 Peripheral Subsystem
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
13
Preliminary