K60P120M100SF2 Datasheet, PDF (60/69 Pages) Freescale Semiconductor, Inc – K60 Data Sheet

Peripheral operating requirements and behaviors
Table 47. I²S master mode timing (continued)
Num
S6
S7
S8
S9
S10
Description
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Min.
Max.
Unit
-2.5
—
ns
—
15
ns
-3
—
ns
20
—
ns
0
—
ns
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
Num
S11
S12
S13
S14
S15
S16
S17
S18
Figure 26. I²S timing — master mode
Table 48. I²S slave mode timing
Description
Operating voltage
I2S_BCLK cycle time (input)
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
Min.
2.7
8 x t_SYS
45%
10
3
—
0
10
2
S6
S10
S8
Max.
3.6
—
55%
—
—
20
—
—
—
Unit
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
K60 Data Sheet Data Sheet, Rev. 6.1, 08/2012.
60
Freescale Semiconductor, Inc.