K60P120M100SF2 Datasheet, PDF (25/69 Pages) Freescale Semiconductor, Inc – K60 Data Sheet

Symbol
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Description
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Min.
Max.
Unit
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1.4
—
ns
—
22.1
ns
—
22.1
ns
100
—
ns
8
—
ns
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
K60 Data Sheet Data Sheet, Rev. 6.1, 08/2012.
Freescale Semiconductor, Inc.
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