K60P120M100SF2 Datasheet, PDF (59/69 Pages) Freescale Semiconductor, Inc – K60 Data Sheet

Num
SD6
SD7
SD8
Peripheral operating requirements and behaviors
Table 46. SDHC switching specifications
(continued)
Symbol Description
Min.
Max.
Unit
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_ISU
SDHC input setup time
t_IH
SDHC input hold time
5
—
ns
0
—
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD1
SD6
SD7
SD8
Figure 25. SDHC timing
6.8.11 I²S switching specifications
This section provides the AC timings for the I²S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 47. I²S master mode timing
Num
S1
S2
S3
S4
S5
Description
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
Min.
2.7
2 x t_SYS
45%
5 x t_SYS
45%
—
Max.
3.6
55%
—
55%
15
Unit
V
ns
MCLK period
ns
BCLK period
ns
Table continues on the next page...
K60 Data Sheet Data Sheet, Rev. 6.1, 08/2012.
Freescale Semiconductor, Inc.
59