56F8365 Datasheet, PDF (58/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym Address Offset
Register Description
ADCA_STAT
ADCA_LSTAT
ADCA_ZCSTAT
ADCA_RSLT 0
ADCA_RSLT 1
ADCA_RSLT 2
ADCA_RSLT 3
ADCA_RSLT 4
ADCA_RSLT 5
ADCA_RSLT 6
ADCA_RSLT 7
ADCA_LLMT 0
ADCA_LLMT 1
ADCA_LLMT 2
ADCA_LLMT 3
ADCA_LLMT 4
ADCA_LLMT 5
ADCA_LLMT 6
ADCA_LLMT 7
ADCA_HLMT 0
ADCA_HLMT 1
ADCA_HLMT 2
ADCA_HLMT 3
ADCA_HLMT 4
ADCA_HLMT 5
ADCA_HLMT 6
ADCA_HLMT 7
ADCA_OFS 0
ADCA_OFS 1
ADCA_OFS 2
ADCA_OFS 3
ADCA_OFS 4
$6
Status Register
$7
Limit Status Register
$8
Zero Crossing Status Register
$9
Result Register 0
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
Result Register 7
$11
Low Limit Register 0
$12
Low Limit Register 1
$13
Low Limit Register 2
$14
Low Limit Register 3
$15
Low Limit Register 4
$16
Low Limit Register 5
$17
Low Limit Register 6
$18
Low Limit Register 7
$19
High Limit Register 0
$1A
High Limit Register 1
$1B
High Limit Register 2
$1C
High Limit Register 3
$1D
High Limit Register 4
$1E
High Limit Register 5
$1F
High Limit Register 6
$20
High Limit Register 7
$21
Offset Register 0
$22
Offset Register 1
$23
Offset Register 2
$24
Offset Register 3
$25
Offset Register 4
56F8365 Technical Data, Rev. 6.0
58
Freescale Semiconductor
Preliminary