56F8365 Datasheet, PDF (47/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Peripheral Memory Mapped Registers
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
CSBAR 0
CSBAR 1
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
CSOR 0
CSOR 1
CSOR 2
CSOR 3
CSOR 4
CSOR 5
CSOR 6
CSOR 7
CSTC 0
CSTC 1
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
$0
Chip Select Base Address Register 0
$1
Chip Select Base Address Register 1
$2
Chip Select Base Address Register 2
$3
Chip Select Base Address Register 3
$4
Chip Select Base Address Register 4
$5
Chip Select Base Address Register 5
$6
Chip Select Base Address Register 6
$7
Chip Select Base Address Register 7
$8
Chip Select Option Register 0
$9
Chip Select Option Register 1
$A
Chip Select Option Register 2
$B
Chip Select Option Register 3
$C
Chip Select Option Register 4
$D
Chip Select Option Register 5
$E
Chip Select Option Register 6
$F
Chip Select Option Register 7
$10
Chip Select Timing Control Register 0
$11
Chip Select Timing Control Register 1
$12
Chip Select Timing Control Register 2
$13
Chip Select Timing Control Register 3
$14
Chip Select Timing Control Register 4
$15
Chip Select Timing Control Register 5
$16
Chip Select Timing Control Register 6
$17
Chip Select Timing Control Register 7
$18
Bus Control Register
56F8365 Technical Data, Rev. 6.0
Freescale Semiconductor
47
Preliminary