56F8365 Datasheet, PDF (115/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.5.6.4 EMI_MODE—Bit 12
This bit controls the pull-up resistors on the EMI_MODE pin.
Note:
In this package, this input pin is double-bonded with the adjacent V_SS pin and this bit should be
changed to a 1 in order to reduce power consumption.
6.5.6.5 RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
6.5.6.6 IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA and IRQB pins.
6.5.6.7 XBOOT—Bit 9
This bit controls the pull-up resistors on the EXTBOOT pin.
Note:
In this package, this input pin is double-bonded with the adjacent V_SS pin and this bit should be
changed to a 1 in order to reduce power consumption.
6.5.6.8 PWMB—Bit 8
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
6.5.6.9 PWMA0—Bit 7
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
6.5.6.10 Reserved—Bit 6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11 CTRL—Bit 5
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.13 JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14 Reserved—Bit 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7 CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. This path has been optimized in order to
minimize any delay and clock duty cycle distortion. All other clocks primarily muxed out are for test
purposes only, and are subject to significant phase shift at high frequencies.
56F8365 Technical Data, Rev. 6.0
Freescale Semiconductor
115
Preliminary