MCF5272 Datasheet, PDF (525/544 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

MBAR
Offset
0x038C
0x0392
0x0394
0x0398
0x039C
MBAR
Offset
0x0840
0x0844
0x0848
0x084C
0x0850
0x0854
0x0880
0x0884
0x08CC
0x08D0
0x08E4
0x08EC
0x0944
0x0948
0x0984
0x0C00
0x0C04
0x0C08
0x0C0C
0x0C10
0x0C14
0x0C18
0x0C40–
0x0DFF
Table A-14. PLIC Module Memory Map (continued)
List of Memory Maps
[31:24]
[23:16]
Aperiodic Interrupt Status Register (PASR)
Reserved
Port0 Sync Delay (P0SDR)
Port2 Sync Delay (P2SDR)
Reserved
[15:8]
[7:0]
Reserved
Loop back Control (PLCR)
D Channel Request (PDRQR)
Port1 Sync Delay (P1SDR)
Port3 Sync Delay (P3SDR)
Clock Select (PCSR)
Table A-15. Ethernet Module Memory Map
[31:24]
[23:16]
[15:8]
Ethernet Control Register (ECR)
Ethernet Interrupt Event Register (EIR)
Ethernet Interrupt Mask Register (EIMR)
Ethernet Interrupt Vector Status (IVSR)
Ethernet Rx Ring Updated Flag (RDAR)
Ethernet Tx Ring Updated Flag (TDAR)
Ethernet MII Data Register (MMFR)
Ethernet MII Speed Register (MSCR)
Ethernet Receive Bound Register (FRBR)
Ethernet Rx FIFO Start Address (FRSR)
Transmit FIFO Watermark (TFWR)
Ethernet Tx FIFO Start Address (TFSR)
Ethernet Rx Control Register (RCR)
Maximum Frame Length Register (MFLR)
Ethernet Tx Control Register (TCR)
Ethernet Address (Lower) (MALR)
Ethernet Address (Upper) (MAUR)
Ethernet Hash Table (Upper) (HTUR)
Ethernet Hash Table (Lower) (HTLR)
Ethernet Rx Descriptor Ring (ERDSR)
Ethernet Tx Descriptor Rin (ETDSR)
Ethernet Rx Buffer Size (EMRBR)
FIFO RAM (EFIFO)
[7:0]
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
A-9